TSMC Reportedly Plans to Raise CoWoS Prices 10% to 20% as AI Demand Tightens Capacity
TSMC is reportedly preparing to raise CoWoS advanced packaging prices by 10% to 20% as surging AI chip demand tightens capacity, stretches equipment delivery times and accelerates a multi-year expansion plan that runs through 2031.
TSMC (TSM) is reportedly preparing to raise prices on its CoWoS advanced packaging by 10% to 20% as surging demand for AI chips tightens capacity, lengthens delivery times and speeds up expansion plans. AI GPUs, server CPUs and custom ASICs are all adding to backlogs, and longer chip-testing times are putting extra pressure on packaging and testing capacity.
Why prices are rising
Packaging has become a bottleneck for the AI buildout. Demand from AI GPUs, server CPUs and custom ASICs keeps growing, and longer testing times tie up capacity at the back end of the process. Equipment is tighter too: delivery times for packaging tools have reportedly stretched from 3–6 months to 6–8 months, and TSMC has reportedly stopped negotiating the annual equipment price reductions it once pushed for, as suppliers prioritize delivery capacity.
TSMC's own comments point the same way. On its Oct. 15 earnings call, management said CoWoS demand remains strong and that it plans to ensure sufficient capacity to meet customers' needs. CEO C.C. Wei called CoWoS customers' top choice for chip assembly. The company raised its 2026 sales growth forecast to about 44% in U.S. dollars and kept 2026 capital spending at $60 billion to $64 billion, saying spending from 2026 to 2028 should exceed the previous three years.
The expansion roadmap
| Period | Reported plan |
|---|---|
| 2026–2027 | CoWoS capacity above 130,000 wafers a month in 2026, targeting 200,000 by 2027. Expansion includes Chiayi AP7, Tainan AP8 and extra SoIC capacity at AP6 |
| 2028 | 14-reticle-size CoWoS supporting 20 HBM stacks, initial CoPoS production and the start-up of the U.S. AP1 advanced packaging facility |
| 2029 | Higher-volume CoPoS, CoWoS supporting 24 HBM stacks, 4.5-micron SoIC technology and lower panel-level packaging costs |
| 2030–2031 | Chiayi's second expansion phase finishes as the third advances, forming a planned 10-factory cluster envisioned as the world's largest advanced packaging hub |
By our calculation, the 2027 target of 200,000 wafers a month is at least 54% above the 130,000 expected for 2026.
Technology and constraints
TSMC says its 5-reticle-size CoWoS is already in mass production with strong yields, while 9x and 14x designs are under development. Larger packages matter because they let more high-bandwidth memory sit next to the processor, which is what AI accelerators need.
Building more capacity is slow. New advanced packaging facilities may need roughly three years to reach full production at the bottleneck stages, and lithography, development, die bonding and equipment availability all limit how fast a ramp can go. That is why price increases and long lead times are likely to persist even as new plants open.
What it means for investors
A price increase on a service that AI chipmakers cannot easily replace supports TSMC's margins, which were 66.4% in the third quarter, and signals that packaging capacity remains the limiting factor for AI accelerator supply. The cost lands on customers building AI GPUs and custom chips, and on equipment suppliers who now have more pricing power. The risk is timing: the large capacity additions arrive in 2027 and beyond, so any easing of the squeeze depends on the ramp staying on schedule.
Sources: Taiwan Semiconductor Manufacturing Company, third-quarter 2026 results (Form 6-K, Oct. 15). The price increase, capacity targets and roadmap are as reported. This is informational, not a recommendation to buy or sell.
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